In order to improve the density of memory devices, the industry has been widely devoted to developing methods to reduce the size of memory cells arranged two-dimensionally. As the memory cell sizes in two-dimensional (2D) memory devices continue to shrink, signal conflict and interference increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, memory devices having a three-dimensional (3D) structure have been developed in the industry to increase the integration density by three-dimensionally arranging the memory cells over the substrate.
Specifically, as shown in FIG. 1A, depositing a multilayer stack structure (for example, a plurality of ONO structures with alternating oxide and nitride) on a substrate; anisotropiclly etching the multilayer stack structure on the substrate to form a plurality of channel vias (which may have direct access to the substrate surface or have a certain over-etch) which are distributed along the extending direction of the memory cell word line (WL) and perpendicular to the substrate surface; depositing polycrystalline silicon or other materials in the channel vias to form a plurality of columnar channels; etching the multilayer stack structure along the WL direction to form a plurality of trenches directly reaching the substrate, exposing a plurality of stacked layers surrounding the columnar channels; wet-removing a certain type of material in the stack (e.g., hot phosphoric acid to remove silicon nitride, or HF to remove silicon oxide) leaving laterally distributed protruding structures around the columnar channels; depositing a gate dielectric layer (e.g., a high-k dielectric material) and a gate conductive layer (e.g., Ti, W, Cu, Mo, and etc) on the sidewalls of the protruding structures in the trenches to form gate stack, which for example, includes a bottom selection gate line BSG, a dummy gate line DG, word lines WL0˜WL31, and a top selection gate line TSG; vertically anisotropic etching to remove the gate stack outside of the protruding plane until the gate dielectric layer on the protruding side is exposed; and then etching the stacked structure to form a source/drain contact and completing the back-end manufacturing process. In this case, a part of the protruding structures left on the sidewall of the columnar channels forms the isolation layers between the gate electrodes, while the remaining gate stack sandwiched between the plurality of isolation layers become control electrodes. When a voltage is applied to the gate, an edge electric field of the gate will make the sidewall of the columnar channels (for example poly silicon material) induced to form a source/drain region, thereby forming a gate array comprised of a plurality of MOSFETs connected in series and/or in parallel so as to record the stored logic status.
However, such a high-density three-dimensional semiconductor memory has a problem of wiring. As shown in the top view of FIG. 1B, in the conventional flash memory chip, the peripheral access circuit and the memory array area are in the same plane, occupying 20-40% of the entire Die area. For high-density memory, compressing the area of peripheral access circuitry becomes a key issue in flash memory design. In the 3D NAND memory shown in FIG. 1A, although the density can be increased by adding the number of layers of the flash memory, the reduction of the peripheral access circuit area has been relatively difficult. Especially for the TCAT structure based on hole-reasing, it is difficult to integrate the memory array area above the peripheral access circuit to reduce the area occupied by the peripheral circuit because of the substrate, as shown in the top view of FIG. 1C.